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| DATA SHEET MOS INTEGRATED CIRCUIT PD444001 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT Description The PD444001 is a high speed, low power, 4,194,304 bits (4,194,304 words by 1 bit) CMOS static RAM. Operating supply voltage is 5.0 V 0.5 V. The PD444001 is packaged in 32-pin PLASTIC SOJ. Features * 4,194,304 words by 1 bit organization * Fast access time : 10, 11, 12 ns (MAX.) * Output Enable input for easy application * Single +5.0 V power supply Ordering Information Part number Package Access time ns (MAX.) Supply current mA (MAX.) At operating 170 160 150 At standby 10 PD444001LE-10 PD444001LE-11 PD444001LE-12 32-pin PLASTIC SOJ (10.16 mm (400)) 10 11 12 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14947EJ4V0DS00 (4th edition) Date Published May 2002 NS CP(K) Printed in Japan The mark shows major revised points. (c) 2000 PD444001 Pin Configuration (Marking Side) /xxx indicates active low signal. 32-pin PLASTIC SOJ (10.16 mm (400)) A0 A1 A2 A3 A4 A5 /CS VCC GND DIN /WE A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A21 A20 A19 A18 A17 A16 /OE GND VCC DOUT A15 A14 A13 A12 A11 NC A0 - A21 : Address Inputs DIN DOUT /CS /WE /OE VCC GND NC : Data Input : Data Output : Chip Select : Write Enable : Output Enable : Power supply : Ground : No connection Remark Refer to Package Drawing for the 1-pin index mark. 2 Data Sheet M14947EJ4V0DS PD444001 Block Diagram Address buffer A0 | A21 Row decoder Memory cell array 4,194,304 bits DIN Input data controller Sense amplifier / Switching circuit Column decoder Output data controller DOUT Address buffer /CS /OE /WE VCC GND Truth Table /CS H L L L /OE /WE Mode Not selected Read Write Output disable I/O High impedance DOUT DIN High impedance Supply current ISB ICC x L x H L H x H Remark x : Don't care Data Sheet M14947EJ4V0DS 3 PD444001 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition Rating -0.5 Note to +7.0 -0.5 Note Unit V V to VCC+0.5 0 to 70 -55 to +125 C C Note -2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 4.5 2.2 -0.5 0 Note TYP. 5.0 MAX. 5.5 VCC + 0.5 +0.8 70 Unit V V V C Note -2.0 V (MIN.) (pulse width : 2 ns) 4 Data Sheet M14947EJ4V0DS PD444001 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Input leakage current Output leakage current Symbol ILI ILO Test condition VIN = 0 V to VCC VOUT = 0 V to VCC, /CS = VIH or /OE = VIH or /WE = VIL Operating supply current ICC /CS = VIL, IOUT = 0 mA, Minimum cycle time Standby supply current ISB ISB1 Cycle time : 10 ns Cycle time : 11 ns Cycle time : 12 ns 170 160 150 40 10 mA mA MIN. -2 -2 TYP. MAX. +2 +2 Unit A A /CS = VIH, VIN = VIH or VIL /CS VCC - 0.2 V, VIN 0.2 V or VIN VCC - 0.2 V High level output voltage Low level output voltage VOH VOL IOH = -4.0 mA IOL = +8.0 mA 2.4 0.4 V V Remark VIN : Input voltage VOUT : Output voltage Capacitance (TA = 25 C, f = 1 MHz) Parameter Input capacitance Output capacitance Symbol CIN COUT VIN = 0 V VOUT = 0 V Test condition MIN. TYP. MAX. 6 8 Unit pF pF Remarks 1. VIN : Input voltage VOUT : Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M14947EJ4V0DS 5 PD444001 AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time 3 ns) Output Waveform Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2. Figure 1 (for tAA, tACS, tOE, tOH) Figure 2 (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW) Remark CL includes capacitances of the probe and jig, and stray capacitances. 6 Data Sheet M14947EJ4V0DS PD444001 Read Cycle Parameter Symbol MIN. Read cycle time Address access time /CS access time /OE access time Output hold from address change /CS to output in low impedance /OE to output in low impedance /CS to output in high impedance /OE to output hold in high impedance tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 3 3 0 5 5 10 10 10 5 3 3 0 6 5 -10 MAX. MIN. 11 11 11 5 3 3 0 6 6 -11 MAX. MIN. 12 12 12 6 -12 MAX. ns ns ns ns ns ns ns ns ns 2, 3 1 Unit Notes Notes 1. See the output load shown in Figure 1. 2. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are periodically sampled and not 100% tested. Read Cycle Timing Chart 1 (Address Access) Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS = /OE = VIL Data Sheet M14947EJ4V0DS 7 PD444001 Read Cycle Timing Chart 2 (/CS Access) Caution Address valid prior to or coincident with /CS low level input. Remark In read cycle, /WE should be fixed to high level. 8 Data Sheet M14947EJ4V0DS PD444001 Write Cycle Parameter Symbol MIN. Write cycle time /CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup time Write recovery time /WE to output in high impedance Output active from end of write tWC tCW tAW tWP tDW tDH tAS tWR tWHZ tOW 3 10 7 7 7 5 0 0 1 5 3 -10 MAX. MIN. 11 7.5 7.5 8 5 0 0 1 5 3 -11 MAX. MIN. 12 8 8 8 6 0 0 1 6 -12 MAX. ns ns ns ns ns ns ns ns ns ns 1, 2 Unit Notes Notes 1. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are periodically sampled and not 100% tested. Data Sheet M14947EJ4V0DS 9 PD444001 Write Cycle Timing Chart 1 (/WE Controlled) Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to DOUT while DOUT is in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. 2. When /WE is at low level, the DOUT pin is always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the DOUT pin high impedance. 10 Data Sheet M14947EJ4V0DS PD444001 Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS /CS (Input) tAW tWP /WE (Input) tCW tWR tDW DIN (Input) Data in tDH High impedance DOUT (Output) Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to DOUT while DOUT is in the output state. Remark Write operation is done during the overlap time of a low level /CS and a low level /WE. Data Sheet M14947EJ4V0DS 11 PD444001 Package Drawing 32-PIN PLASTIC SOJ (10.16mm (400)) B 32 17 C D 1 G J F E 16 U S Q S T M K I H N M P NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM B C D E F G H I J K M N P Q T U MILLIMETERS 21.260.2 10.16 11.180.2 1.0050.1 0.74 3.50.2 2.5450.2 0.8 MIN. 2.6 1.27(T.P.) 0.400.10 0.12 9.40.20 0.1 R0.85 0.20 +0.10 -0.05 P32LE-400A-1 12 Data Sheet M14947EJ4V0DS PD444001 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD444001. Type of Surface Mount Device PD444001LE : 32-pin PLASTIC SOJ (10.16 mm (400)) Data Sheet M14947EJ4V0DS 13 PD444001 Revision History Edition/ Date 4th edition/ May 2002 Page This edition p.1, 2, 12, 13 Previous edition p.1, 2, 13, 14 Type of revision Location Description (Previous edition This edition) Deletion Ordering Information, Pin Configuration, Package Drawing, Type of Surface Mount Device 32-pin PLASTIC TSOP (II) p.5 p.5 Deletion Modification DC Characteristics Capacitance Read Cycle, Write Cycle Remark2 Remark2 Note3 Remark p.7, 9 p.7, 9 Modification Deletion 14 Data Sheet M14947EJ4V0DS PD444001 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14947EJ4V0DS 15 PD444001 * The information in this document is current as of May, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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